The present invention relates to improving the permitted amount of nominal signal delay through an LSI circuit.
In conventional systems, a system clock signal is often used by digital circuitry, such as digital circuitry implemented using a LSI circuit, to synchronously execute certain logic functions. For example, ultra-deep sub-micron (UDSM) microprocessors employ digital circuitry that uses system clock signals to synchronously execute logic functions. These microprocessors operate at system clock frequencies of 1-10 GHz and higher. The system clock signal of a given LSI circuit is often split into many paths to service many different portions of the digital circuitry.
Complex LSI circuits include multiple distinct circuit areas, each with its own path from input to output, and each with the need for a system clock signal to clock the signals through digital circuitry. Depending on the function of the LSI, some circuit areas are cascaded in series and others are arranged in parallel. In general, in order for the circuit areas to operate properly, the synchronous design of the LSI must satisfy the following condition between clock cycle time (T) and circuit delay time (D): T≧D. In practice, the clock cycle time of the system clock should be significantly greater than the delay of a signal through a given circuit area of the LSI.
The problem in prior art LSI circuits is that variations in the power supply voltage of the LSI have a negative effect on the permitted nominal signal delay through the LSI circuit. This results in higher power consumption in the LSI and has placed a burden on designers of LSI circuits to keep the nominal signal delay as small as possible, thereby driving up costs.